The electronics field is becoming more competitive. New entrants to the market are generating tremendous pressure to increase efficiency of logic design, to reduce design cost, and, to reduce time to market. Extensive performance of simulation can detect design errors before a design is manufactured, and thus reduce the number of design iterations. The use of an efficient hardware description language (HDL) such as VERILOG.RTM. and a host simulation system has become invaluable for minimizing design errors, and has made it possible to fabricate functional chips in the first silicon processed.
Computers, used as a host for a logic simulation program, in one example, employ a hierarchical information retrieval method for transferring information or data between storage devices. One of the storage devices is typically a mass storage device, such as a hard disk. Another of the storage devices usually comprises a relatively faster and more accessible storage device such as random-access memory (RAM). Finally, an intermediate storage device, such as a cache on a microprocessor, is used to provide rapid, but usually very small, data transfers between the hard disk and random-access memory. The random-access memory is normally smaller than a hard disk and is usually a faster and more accessible storage device The relative size between the cache and the random-access memory varies. On a personal computer, the cache is usually smaller than the random access memory. On workstations and microcomputers, the cache is usually larger than the random access memory. Such a pattern commonly exists notwithstanding a use of multiple levels of hierarchy.
Common retrieval methods employ paging, swapping, or caching to improve the utilization storage devices by reversibly transferring large blocks of information between the storage devices. While these retrieval methods normally improve the efficiency of a logic simulation program, that improved efficiency is merely a side effect rather than an intended purpose.
In prior logic simulation programs, the host simulation system uses a static memory allocation algorithm in the hardware description language, VERILOG, which requires the employment of a random-access memory (hereinafter referred to as a "memory array") of a size at least equal to the entire simulated memory size. Thus, the permitted size of information or data transfers is determined largely by the physical size of the memory array. If, for example, a 128 megabit hard memory device is called for by the logic simulation program and the memory array has enough capacity, the entire contents of the hard memory device is transferred into the memarray. This can create substantial inefficiencies, especially with hard memory devices that are large.
Prior logic simulation programs are limited to either using expensive, large memory arrays or performing the time-consuming operation of transferring the contents of relatively small increments of memory to the memory array, regardless of the usefulness of a particular memory increment. A need exists for a logic simulation program that does not use a full memory transfer like that utilized by the static memory allocation algorithm. Accordingly, the present invention provides a dynamic memory allocation algorithm for the hardware description language, i.e., VERILOG, that adjusts the amount of data transferred to the memory array, and, for example, can transfer less than the entire contents of a hard memory device in a logic simulation program. Fewer data transfers are made to the memory array. Thus, the total size of the data transferred to the memory array, in a logic simulation program employing the present invention the present invention, is a much smaller than the entire size of the memory that is simulated.